1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to methods of forming a metal interconnect on an IC chip and the IC chip including the metal interconnect.
2. Background Art
In the integrated circuit (IC) chip fabrication industry, there are three sections referred to in a typical IC chip build: front end of the line (FEOL), back end of the line (BEOL) and the section that connects those two together, the middle of the line (MOL). The FEOL is made up of the semiconductor devices, e.g., transistors, the BEOL is made up of interconnects and wiring, and the MOL is an interconnect between the FEOL and BEOL that includes material to prevent the diffusion of BEOL metals to FEOL devices.
The FEOL transistor devices are typically processed using single crystal and poly-crystalline silicon. The BEOL interconnects are typically made of multiple metals; the bulk of the conductor is copper. If copper diffuses into the FEOL silicon based devices it can cause shorting or alter sensitive transistor characteristics and render the semiconductor useless. This is the reason for the MOL connection. This connection is usually made of tungsten. Although tungsten has a higher resistivity compared to other metals, its ability to prevent copper diffusion while still maintaining high conductivity is extremely desirable. The insulator that the MOL resides in is a higher dielectric constant (high-k, e.g., >3.9) value than the BEOL insulator. The dielectric constant value of the insulator is one major factor that determines the speed at which the signals can travel in that conductor. The high-k MOL insulator is necessary because of its close proximity to the FEOL devices. The high-k MOL insulator is used for various manufacturing issues that are well known in the art.
One challenge relative to current technology is that when the BEOL first metal layer (M1) is processed, typically some portion of the metal line resides in the high-k MOL insulator. That is, the metal protrudes into the high-k MOL insulator, perhaps surrounding a MOL layer contact. Accordingly, the trend of the industry towards low-k materials (e.g., k<3.9) for BEOL insulators is severely hampered by the first line level residing in a high-k insulating material. In particular, any advantage gained by using low-k dielectric is lost for at least the first metal layer of the BEOL by the above situation.
One approach to address this situation is to use a thin layer of high-k dielectric around the contacts of the MOL layer with a low-k material (e.g., hydrogenated silicon oxycarbide (SiCOH)) over the high-k dielectric.
Unfortunately, contact materials typically used in the MOL layer (e.g., tungsten) usually require an aggressive planarizing process, which easily damages the less physically robust low-k material.